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BackConversation # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Latest commits for branch hard_sync Merge pull request synth_mages/MK_VCO#5 613d1b6f7e Merge pull request 'pcb_finalization' (#1) from pcb_finalization into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Merge pull request synth_mages/MK_VCO#5 613d1b6f7e Merge pull request synth_mages/MK_VCO#5 Merge pull request.
- 9.695134e+01 1.105996e+01 facet normal.
- Bat + 7 + 8); .
- 3143 .../Unseen Servant/Unseen Servant.kicad_sch | 30.
- 3.54289 8.26214 3.82299 facet normal -1.413055e-15 -1.598987e-15 -1.000000e+00.
- 1.627112e+000 2.470218e+001 facet normal 0.0822199.