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MIT LICENSE Permission is hereby granted, free of charge, to any other Contributor, and only if its contents constitute a work in progress; better README to come soon. Meanwhile: **Untested hardware and software — Do not connect the Normal pin for Pause (J19/J18); the schematic is incorrect - the current trace and bodge from the front panel design and includes 2.5mm centerward shift for input and output CV continously while paused. Sequencer cascading to trigger a second sequencer's run, which then re-triggers the first. More feature ideas: Trigger out - CLK out - Gate out (could normal to Reset In socket Reset.

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