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BackCompressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 0 Minor layout tweaks merged pull request 'More schematics' (#3) from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file tstamp 52a45927-621d-4774-9080-e26ba88e3d95) Final revision; added custom DRC as project file 8976a63dc06fa25beedf8d2553931872c491047e adds README.md file again gets comfier with gitignore and git rm --cache fp-info-cache | 91876 1 file changed, 91876 deletions(-
- -3.215698e-01 0.000000e+00 vertex -9.698088e+01.
- Pin (https://www.st.com/resource/en/datasheet/l7980.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py.
- Normal -1.296024e-14 -1.000000e+00 -2.688893e-15 vertex -1.043143e+02.
- Normal 0.964172 0.255778 -0.0703594 vertex 7.87145.
- Livestream - avoid non-circular holes in.