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Stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape.

• 5.869991e-001 vertex 4.096884e+000 2.346750e+000.
• Diameter 1.8mm, hole diameter 2.0mm.
• Fuse 0ZRE0012FF, BelFuse, Radial.

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