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Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4.

FBV484 Artix-7, Kintex-7 and Zynq-7000 BGA, 34x34.
Connector, B10P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator crystal.
Audio_jack_3_5mm() { } module title(string, size=12.
-0.538537 0.705981 facet normal.

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