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Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= b1fcba1e78f37669542b35a3e32a5257c5c0240c 531ebcae92ad8ad00635060e3583259ee13cc12b 5ff3077e8252367b7eceb0b21b0803904b695d42 Fix.

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