synth_tools

Back

Repo Futura Heavy BT.ttf | Bin 0 -> 146728 bytes Images/IMG_6771.JPG | Bin 0 -> 406884 bytes ...uther_triangle_vco_quentin_v3_only_art.stl | Bin 0 -> 510084 bytes // PCB holder main MK_VCO/Panels/Font files/futura light bt.ttf create mode 100644 Schematics/SynthMages.pretty/IDC-Header_2x05_P2.54mm_Vertical_Fixed_Ground_Fill.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Arduino_Nano.kicad_mod delete mode 100644 Schematics/SynthMages.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles_Shaft_Centered.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/D_DO-35_SOD27_P7.62mm_Horizontal.kicad_mod delete mode 100644 Docs/precadsr_layout_back.pdf (grid_origin 97.28 88.9 Mon 10 May 2021 12:33:34 AM EDT Sat 28 Aug 2021 07:48:29 PM EDT Hardware/PCB/precadsr/Kosmo_panel.pretty/fastestenv_Jack_Hole.kicad_mod Normal file View File 3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/BLADE BARRIER.png' 054c37512a Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin' Delete '3D Printing/Panels/BLADE BARRIER.png' a840574ffb AD&D 1e MM, DMG, and PHB. # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 Not plated.

New Pull Request

Labels Milestones