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BackDate Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Finished PCB, passes all passable DRCs created pull request synth_mages/MK_VCO#5 Final revision; added custom DRC as project file ) ) Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file.
- -2.608102e-001 0.000000e+000 vertex -3.363539e+000.
- 0.946346 -0.307482 0.0994132 facet normal -0.000419123.
- Converters dc-dc recom buck.
- SPT 5/8-H-7.5-ZB Terminal Block, 1732399 (https://www.phoenixcontact.com/online/portal/gb/?uri=pxc-oc-itemdetail:pid=1732399), generated with.
- -0.866022 0 vertex -8.47298 -5.66146 0 vertex.