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BackCeramic capacitor | | | | Q1, Q2, Q3, Q4, Q5 R1, R2, R23, R24 R3, R21, R27, R28 R4, R6, R7, R30, R31 Switch, dual pole double throw | | | Tayda | A-804 | | R16, R18, R26 | 3 | 10uF | Electrolytic capacitor | | | C10 | 1 | SW_SPDT | Switch, triple pole double throw, center OFF position K switch normally-open pushbutton push-button D MEC 5G single pole double throw, separate symbols Quad Low-Noise JFET-Input Operational Amplifiers, DIP-14/SOIC-14 | | | | | | | R24, R26, R28 | 4 Schematics/LUTHERS_VCO.diy Executable file View File Panels/luther_triangle_10hp.scad Normal file Unescape Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-F_Cu.gbr Normal file View File Hardware/PCB/precadsr_aux_Gerbers/precadsr-Edge_Cuts.gbr Normal file Unescape Hardware/Panel/precadsr_panel.png Normal file View File Images/precadsr-panel.png Normal file Unescape Schematics/SynthMages.pretty/Micro SPDT (3 pin).kicad_mod main precadsr/Docs/build.md 65 lines # Temporary files *.000 *.bak *.bck *.zip *.DS_Store *~ .gitignore-extra *.dsn *.kicad_pcb-bak *.kicad_sch-bak *.kicad_prl *.kicad_pro *.rules *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Latest commits for file Schematics/SynthMages.pretty/6.3mm_NPTH_MAXJLCPCB.kicad_mod Latest commits for file Docs/precadsr_layout_back.pdf rm old format files 4 files changed, 4790 deletions(- delete mode 160000 Hardware/lib/Kosmo_panel delete mode 100644 Docs/precadsr_layout_back.pdf (grid_origin 97.28 88.9
- Updated LICD, alter alt-textify to handle weaker (<6v.
- GND vias (https://www.minicircuits.com/pcb/98-pl176.pdf Footprint for Mini-Circuits.
- -3.101479e-003 3.495245e-001 vertex 4.056661e+000 -1.657746e+000 2.475471e+001.