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Transistor footprint to inline_wide, fix DRC ground plane Updates from real TL0x4, fix pots being backwards, tighten up schematic, fit letter instead of latch, https://www.neutrik.com/en/product/nc3faah1-0 AA Series, 3 pole male XLR receptacle, grounding: separate ground contact connected to EP (http://www.aosmd.com/res/packaging_information/DFN5x6_8L_EP1_P.pdf 56-Lead Plastic Quad Flat, No Lead Package - 4.0x4.0x0.8 mm Body [QFN] with corner pads; see figure 8.2 of https://www.silabs.com/documents/public/data-sheets/efm8bb1-datasheet.pdf 20-Lead Plastic Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [HTSSOP], with thermal vias in pads, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py 4-Lead Plastic Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/83831/lh1533ab.pdf SSO Stretched SO SOIC Pitch 2.54 SSO Stretched SO SOIC Pitch 2.54 SSO Stretched SO SOIC 2.54 8-Lead Plastic Small Outline.

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