Labels Milestones
Back1943 40 Dwgs.User user hide (35 F.Paste user (36 B.SilkS user (37 F.SilkS user hide (0 "F.Cu" signal (31 B.Cu signal (32 B.Adhes user (33 F.Adhes user (34 B.Paste user (35 F.Paste user (36 B.SilkS user (37 F.SilkS user hide (42 Eco1.User user hide (48 B.Fab user hide From 713014315986726ad96f361cfbc8e67551a6a879 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add ground fills, fix some clearance issues, make all power traces large "rules": { PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces Fireball/Fireball.kicad_prl | 2 | 10k | Resistor | | R25 | 1 | 2_pin_Molex_connector | 2 | 4.7k | Resistor | | | | | R14, R15, R18 | 3 | 10 uF tantalum\nMFOS 1, 1+15 electrolytic\n1 uF tanty looks better than EL\n(higher output, less leakage)\nbut only by a little. 1 µF \npolyester film looks much \nbetter. Low-Power, Quad-Operational Amplifiers, DIP-14/SOIC-14/SSOP-14
New Pull Request