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Fix pots going the wrong way

change footprints of transistors to save on panel wires fewer_panel_wires Latest commits for file Images/IMG_6770.JPG Binary files a/Panels/title_test.stl and b/Panels/title_test.stl differ Binary files /dev/null and b/Synth_Manuals/Module Summaries.ods differ Binary files a/3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/POLYMORPH.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin typeface 900028d3cf Futura BT font files ... Delete 'Panels/futura medium condensed bt.ttf' ## Current draw 12 mA +12 V, and sustain voltage is taken from \npot pin 1 x 1 mm, 734-150 , 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator JST ZE series connector, LY20-38P-DT1, 19 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator Hirose FH12, FFC/FPC connector, FF0829SA1, 29 Circuits (https://www.molex.com/pdm_docs/sd/2005280290_sd.pdf), generated with kicad-footprint-generator Molex CLIK-Mate series connector, B24B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator Molex CLIK-Mate series connector, S5B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator Hirose DF13 through hole, DF13-08P-1.25DS, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated.

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