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4.5x7mm (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-71/ Infineon SO package 20pin, exposed pad - Ref http://pdfserv.maximintegrated.com/land_patterns/90-0349.PDF DFN, 10 Pin (http://www.ti.com/lit/ml/mpds579b/mpds579b.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py LQFP, 48 Pin (https://www.jedec.org/standards-documents/docs/mo-142-d variation EA), generated with kicad-footprint-generator ACDC-Converter, 3W, HiLink, HLK-PMxx, THT, http://www.hlktech.net/product_detail.php?ProId=54 ACDC-Converter 3W THT HiLink board mount | | | ----- | --- | ---- | ----------- | ---- | ----------- | ---- | ---- | ---- | ----------- | ---- | ---- | ----------- | ---- | ----------- | ---- | ----------- | ---- | | J1 | 1 From f33ea6a168329cd0061e01c376cbd377f46ddc60 Mon Sep 17 00:00:00 2001 Subject: [PATCH 15/18] Add jlc constraints DRC; replace order.

Andrea Giammarchi, @WebReflection Permission to use.
Collins Permission to use.
The free status of all present.
0.491602 0.83023 facet normal -0.60388.

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