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Floating pin for Pause (J19/J18); the schematic and PCB, no warnings d62e7c6861 More work finding space for well-aligned, well-printed numbers // step rotary switch to set output voltages. (10 - One SPDT switch to disable reset (run once). Momentary-normal-off pushbutton to manually reset. More repo cleanup, adopt github .gitignore file 8976a63dc06fa25beedf8d2553931872c491047e adds README.md file afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file (pts Final revision; added custom DRC as project file 666c48f795106664bf9f1401667d0a4bc7a85e2a updates led holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf 25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes distance 63.5mm Hirose FH12, FFC/FPC connector, FH12-20S-0.5SH, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py Nexperia wafer level chip-size package; 15 bumps (6-3-6), 2.37x1.17mm, 15 Ball, 6x3 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g031y8.pdf ST WLCSP-20, ST die ID 467, 3.09x3.15mm, 52 Ball, X-staggered 21x11 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32l562ce.pdf ST WLCSP-90, ST die ID 479, 3.56x3.52mm, 64 Ball, 8x8 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32wb15cc.pdf#page=119 ST WLCSP-52, ST die ID 460, 2.3x2.48mm, 25 Ball, 5x5 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32wb15cc.pdf#page=119 ST WLCSP-52, ST die ID 467, 3.09x3.15mm, 52 Ball, X-staggered 7x5 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32l562ce.pdf ST WLCSP-90, ST die ID 479, 3.56x3.52mm, 64 Ball, 8x8 Layout, 0.4mm Pitch, https://www.ti.com/lit/ml/mxbg419/mxbg419.pdf, https://www.ti.com/lit/ds/symlink/tmp117.pdf Texas Instruments, BGA Microstar Junior, 2x2.5mm, 12 bump 3x4 (area) array, NSMD pad definition Appendix A Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=301, NSMD pad definition Appendix A BGA 676 1 FF676 FFG676 FFV676 Kintex-7 and Zynq-7000 BGA, 20x20 grid, 17x17mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=270, NSMD pad definition Appendix A BGA 1156 1 FF1157 FFG1157 FFV1157 FF1158 FFG1158 FFV1158 Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=277, https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=296, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=91, NSMD pad definition Appendix A BGA 256 1 FT256 FTG256 Spartan-7 BGA, 15x15 grid, 13x13mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 UFBGA-15, 4x4, 3x3mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf.

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