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BackSimulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= b1fcba1e78f37669542b35a3e32a5257c5c0240c Panels/luther_triangle_vco_quentin_v2.scad Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Arduino_Nano.kicad_mod Normal file View.