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BackDrill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 147621.
- Circle. Used only where.
- 4.412147e-001 8.609716e-001 vertex -4.144307e+000 -2.460357e+000 2.493625e+001.