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*.kicad_pcb-bak *.kicad_sch-bak *.kicad_prl *.kicad_pro *.rules *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Netlist files (exported from Pcbnew) Initial version .gitignore | 1 | B10k | Potentiometer | | U2 | 1 | LED | Light emitting diode | | R15, R17, R19 | 2 Hardware/lib/Kosmo_panel | 2 | 10k | Resistor | | | R3, R21 | 2 .../Unseen Servant/Unseen Servant.kicad_pcb | 31887 .../Unseen Servant/Unseen Servant.kicad_sch | 166 Add position for resistor between coarse and +12V, value unknown Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane Change transistor footprint to inline_wide, fix DRC ground plane 5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request synth_mages/MK_VCO#2 21e2abea62 Merge pull request synth_mages/MK_VCO#4 24955050f1 Merge pull request 'More schematics' (#3) from schematic into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/2 Merge pull request 'pcb_finalization' (#1) from bugfix/10hp into main ... Add jlc constraints DRC; replace order number text Compare 19 commits » 2bd01a1ff2 Add schematic, start on PCB with exploratory 8hp layout PSU/Synth Mages Power Word Stun Panel.kicad_pcb | 1070 Synth Mages Power Word Stun.kicad_pcb create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Arduino_Nano.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/DIP-14_W7.62mm_Socket_LongPads.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x08_P2.54mm_Vertical.kicad_mod create mode 100644 Docs/precadsr_layout_back.pdf (grid_origin 97.28 88.9 Mon 10 May 2021 12:33:34 AM EDT **Component Count:** 74 **Component Count:** 74 Latest commits for file Schematics/bad_trace_v1.jpeg add pic Schematics/bad_trace_v1.jpeg | Bin 0 -> 38860 bytes Panels/Font files/futura medium bt.ttf differ Binary files /dev/null and b/Panels/title_test_22.stl differ Binary files /dev/null and b/Images/IMG_6770.JPG differ Binary files /dev/null and b/Panels/futura medium bt.ttf | Bin 0 -> 121262 bytes Panels/FireballSpell_Large_bw.png | Bin 0 -> 328607 bytes Images/PXL_20210831_001017829.jpg | Bin 0 -> 38860 bytes Panels/Font files/futura medium bt.ttf | Bin 11675 -> 0 bytes Notes: Before producing, confirm footprint dimensions for capacitors, diodes (inc. LEDs), and barrel power jack works physically for male connector from wall wart. - Consider adding a switch to set output voltages. (10 One potentiometer for internal clock rate. Binary files.