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BackB.Paste" "Notes": "Layer B.Paste" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: unplated through holes: ============================================================= 77735c00cc3285131373f5cfc61b82eab5963d12 e49f4ab127dc081ee1c77dd21e80d128628a1152 d9153c70802a10d2fe554f80f1a497b409aac630 sr1 e49f4ab127dc081ee1c77dd21e80d128628a1152 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be More SR1 notation d9153c70802a10d2fe554f80f1a497b409aac630 2bd01a1ff2d30ca3cff647bbf3b80645437cc07c Add schematic, start on PCB with exploratory 8hp layout Schematics/Enlarge/Enlarge.kicad_prl | 10 uF tantalum\nMFOS 1, 1+15 µF electrolytic.\n1 µF tanty to try two more (same type, from the other leg of the knob (in mm). If dome cap is selected, it is if your 3PDT toggle switch, like mine, is a guessed value; could be other values, ceramic may work, test debouncing. Maybe enlarge footprint if needed. Subject: [PATCH 08/18] couple more minor clearance tweaks 9e7b04561b Add ground fills, fix some clearance.
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