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Way to updating the two clockwise-most pins, looking from below. Clock rate goes down when resistance goes up, opposite to expectation. C1 is too small for film; is film needed? More notes More notes move bugs to md file to be +1mm between legs -- Don't put R8 so close to R26 -- D36/R47 too close Testing before powering up: Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 - Clock rate (B100k) (not sure yet which 2 pins Rectangular size 5.0x2.0mm^2 3 pins Ceramic Resomator/Filter Murata CSTCE, https://www.murata.com/en-eu/products/productdata/8801162264606/SPEC-CSTNE16M0VH3C000R0.pdf SMD SMT mems oscillator Analog BGA-49, 6.25x6.25mm, 49 Ball, 7x7 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g0b1ne.pdf#page=136 ST WLCSP-64, ST die ID 495, 4.4x4.38mm, 100 Ball, 10x10 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g0b1ne.pdf#page=136 ST WLCSP-64, ST die ID 468, 3.15x3.13mm, 49 Ball, 7x7 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=25 FBGA-78, 10.5x9.0mm, 78 Ball, 9x13 Layout, 0.8mm Pitch, https://www.ti.com/lit/ml/mpbg777/mpbg777.pdf BGA 289 0.8 ZAV S-PBGA-N289 Texas Instruments, DSBGA, area grid, YBG pad definition, 0.95x1.488mm, 6 Ball, 2x3 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g0b1ne.pdf#page=136 ST WLCSP-64, ST die ID 482, 4.2x3.95mm, 90 Ball, X-staggered 21x11 Layout, 0.4mm Pitch, https://pdfserv.maximintegrated.com/package_dwgs/21-100489.PDF WLCSP-25, 5x5 raster, 2.133x2.070mm package, pitch 0.35mm; https://datasheets.maximintegrated.com/en/ds/MAX40200.pdf WLP-9, 1.448x1.468mm, 9.

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