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750478ab8360c0ef45b55687504a3e4846b752b4 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Finished PCB, passes all passable DRCs created pull request 'new_footprints' (#5) from new_footprints into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file tstamp 42deceed-4793-4b11-91d8-f336ff75a562) Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file tstamp 52a45927-621d-4774-9080-e26ba88e3d95) Final revision; added custom DRC as project file tstamp 52a45927-621d-4774-9080-e26ba88e3d95) Final revision; added custom DRC as project file new_footprints Added hard sync to schematic, laid out PCB with on-board Fireball/Fireball.kicad_pcb | 8194 Fireball/Fireball_panel.kicad_pro | 6 From f51b7b97734e404127fa5d5d263acbfd66f116e4 Mon Sep 17 00:00:00 2001 Subject: [PATCH 09/13] Notes from MK's PCB livestream # Format documentation: https://kicad.org/help/file-formats/ # Netlist files (exported from Pcbnew *.ses # Exported BOM files *.xml *.csv # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Apply jlcpcb's design rules, small fixes for those couple more minor clearance tweaks Subject: [PATCH 11/13] more fixes PSU/Synth Mages Power Word Stun Panel.kicad_prl | 77 Fireball/Fireball_panel.kicad_pro | 504 Fireball/fp-info-cache | 36 ...gson_DG301_1x03_P5.00mm_Vertical.kicad_mod | 63 3D Printing/Panels/Radio_shaek_standoff.stl | Bin 0 -> 37432 bytes Panels/futura medium bt.ttf differ Binary files /dev/null and b/3D Printing/Rails/36hp_innie.stl differ Binary files /dev/null and b/3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/FIREBALL VCO.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin' b96c823428337e1169ae4a0f1d50e46562744447 Add '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/PRISMATIC SPHERE.png From 943ef1409b7317dabcc4b76bf70a2fada90d2c4f Mon Sep 17 00:00:00 2001 Subject: [PATCH] Initial kicad, images, gitignore for kicad backups *-backups More repo cleanup, adopt github .gitignore file .gitattributes From 9f0e0a275be19d54acb7a510415f15c04cb49983 Mon Sep 17 00:00:00 2001 Subject: [PATCH] To GitLab Hardware/PCB/precadsr/precadsr.kicad_pcb | 3 pin Molex connector 2.54 mm spacing R23, R24, R25, R27 .

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