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Back*~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH 08/13] More notes Schematics/schematic_bugs_v1.txt | 2 | 1N5817 | Schottky diode | Tayda | A-3186 | | | | U3 | 1 | Synth_power_2x5 | 2x5 pin shrouded header 2.54 mm spacing
- Jacks bottom_row = v_margin .
- Normal -6.797594e-001 -2.793198e-003 7.334298e-001 vertex 4.136113e+000 -2.387214e+000 2.488918e+001.
- 5.08mm length 14.5mm diameter 5.8mm Fastron HBCC Inductor.