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Where users want round outlines by specifying ≥30 faces. Quality == "rendering") ? 0.25 : quality == "fast preview") ? 12 : 12; // [1:1:84] /* [Holes] */ hole_dist_top = 2.5; rail_clearance = 8.5; // mm from very top/bottom edge and where it is based on http://www.latticesemi.com/view_document?document_id=213 BGA 0.8mm 9mm 121 BGA-132 11x17 12x18mm 1.0pitch Altera BGA-144 M144 MBGA Altera UBGA U324 BGA-324 BGA-624, 25x25 grid, 21x21mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf WLCSP-81, 9x9 raster, 4.039x3.951mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf WLCSP-36, 6x6 raster, 2.553x2.579mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf WLCSP-143, 11x13 raster, 4.539x5.849mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf UFBGA 132 Pins, 0.5mm Pitch, S-PVSON-N10, DRC, http://www.ti.com/lit/ds/symlink/tps61201.pdf 3x3mm Body, 0.65mm Pitch, S-PVSON-N8, http://www.ti.com/lit/ds/symlink/opa2333.pdf 3x3mm Body, 0.5mm Pitch (http://www.ti.com/lit/ds/symlink/lm4990.pdf WSON, 12 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=62), generated with kicad-footprint-generator ipc_gullwing_generator.py SSOP24: plastic shrink small outline package; 44 leads; body width 3.9 mm; lead pitch 0.635; (see NXP sot054_po.pdf TO-126-2, Horizontal, RM 5.08mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf TO-126-3 Horizontal RM 4.58mm IPAK TO-251-2, Vertical, RM 1.7mm, staggered type-1, see http://www.ti.com/lit/ds/symlink/lmd18200.pdf TO-220-15, Vertical, RM 5.08mm, see http://cdn-reichelt.de/documents/datenblatt/A400/W005M-W10M_SEP.PDF diode bridge Vishay KBL rectifier diode bridge Vishay KBU rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88655/kbl005.pdf Vishay KBL.

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