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Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: ============================================================= f51b7b97734e404127fa5d5d263acbfd66f116e4 Bring in diylc and openscad design Add Kick as separate sheet wants to merge 5 commits from bugfix/v1.1 into main.

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