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Href="https://gitea.circuitlocution.com/ /arrasta/commit/2cddc4d62d38c9e1b69839f92a19e7915eecbceb" rel="nofollow">2cddc4d62d38c9e1b69839f92a19e7915eecbceb formatting caixa bits f51b7b97734e404127fa5d5d263acbfd66f116e4 Add schematic, start on PCB with exploratory 8hp layout 0d370a24cdcaf6d3fd7f0316855522b79df0fe9a 3583986e89 Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1. This needs to be fixed elsewhere ec67859b1c Start.

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