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BackMerged pull request synth_mages/MK_VCO#4 merged pull request synth_mages/MK_VCO#5 Final revision; added custom DRC as project file tstamp 52a45927-621d-4774-9080-e26ba88e3d95) Final revision; added custom DRC as project file ) ) New KiCad version; non Al panel Gerbers ) (filled_polygon New KiCad version; non Al panel Gerbers ) (filled_polygon New KiCad version; non Al panel Gerbers *~ New KiCad version; non Al panel Gerbers # Netlist files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4.
- 0.222395 -0.884723 0.409641 facet.
- 0.0703599 facet normal -7.070919e-001 -3.148546e-003 7.071147e-001.
- -0.956976 -0.290168 0 facet normal 2.941706e-004 -5.043191e-004.
- , length*diameter=10*4.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf.