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BackVSON, 10 Pin (www.allegromicro.com/~/media/Files/Datasheets/A4952-3-Datasheet.ashx?la=en#page=10), generated with kicad-footprint-generator JST VH series connector, B10PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py Micro Leadframe Package, 16 pin connector, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F215079%7FY1%7Fpdf%7FEnglish%7FENG_CD_215079_Y1.pdf%7F215079-4 connector TE-Connectivity Micro-MaTch Vertical 1-215079-8 8-215079-18 TE-Connectivity Micro-MaTch female-on-board top-entry thru-hole 14 pin DIP socket | | C13 | 3 From 2118197c1e2cab02a4a0c4b6381e9d7946ff4f12 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add jlc constraints DRC; replace order number text Compare 19 commits » created pull request synth_mages/MK_VCO#7 Updates from real TL0x4s Compare 6 commits » merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main 1705ad98fb Put title box in PDF export' (#4) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 Generated from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 Generated from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file Final revision; added custom DRC as project file c4e1c30b9b Add jlc constraints.
- -0.090682 0.920074 0.381103 vertex.
- Normal -4.308032e-01 -9.024458e-01 -3.431192e-04 vertex -9.446753e+01 1.054761e+02 2.550000e+00.