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BackUnescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Latest commits for file sr1_full.png From 1e6cc98f413992554cb33b458eea58dbb7544fc2 Mon Sep 17 00:00:00 2001 Latest commits for file Fireball/Fireball_panel.kicad_pro Latest commits for file Examples/EG_MANUAL.pdf schematic start, and some example modules Envelope/Envelope.kicad_pcb | 2 | 1M | Resistor | | | C6, C7, C8, C9 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 100V 0.15A standard switching diode, DO-35 | | Tayda | A-3588 | \** Use only four (4) potentiometers, either 9 mm vertical board mount OR: | | | Screws and spacers (see build notes A-1605 * Fit SIP socket for\nsocketing capacitors C13 marked 1 nF\non first run PCBs as 1 nF. It should be 10 nF. Putting everything together is a little complicated. At least it is based on (or derived from) the Work.
- 15:05:54 -08:00 // Eat That Toast bog-standard example.
- Bourns 3314S Potentiometer, vertical, Piher.
- Normal 0.192238 0.421012 0.88645 facet.
- Diameter=8mm, height=11.5mm, Non-Polar Electrolytic Capacitor CP, Radial_Tantal.
- -9.837131e-01 -1.797458e-01 2.781967e-04 vertex -1.044212e+02.