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-5.040221e-01 8.636908e-01 1.027001e-04 vertex -1.011809e+02 1.050104e+02 4.255000e+01 facet normal 0.264755 0.918689 0.293113 vertex 4.78188 4.20094 7.71954 facet normal 9.286611e-01 4.719780e-04 -3.709291e-01 vertex -9.041368e+01 1.006749e+02 1.197185e+01 facet normal 0.881921 0.471397 0 vertex -1.98804 9.99456 0 facet normal 0.499999 -0.866026 6.96236e-08 vertex -2.35938 1.82407 11.0482 facet normal -0.0816274 -0.0817217 0.993307 vertex -5.16186 -5.26759 6.86461 vertex 5.23616 -5.23616 6.86814 facet normal 9.995641e-01 2.473940e-03 -2.941899e-02 facet normal 4.328695e-01 5.487434e-03 9.014399e-01 facet normal 7.741848e-01 1.163684e-03 -6.329586e-01 vertex -1.053126e+02 9.725134e+01 1.053895e+01 facet normal -0.111555 0.367742 0.923212 vertex -2.64292 8.55797 3.82299 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 v1.0 Add CV in implement a DC offset via non-inverting op-amp. A CV in to pause the clock Add CV.

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