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Back'track'" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: merged pull request 'More schematics' (#3) from schematic into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/3 Merge pull request synth_mages/MK_VCO#5 b554ec2138 Add footprint items for panel holes; separate panel and pcb into different files Add a front-panel.
- 9.725134e+01 1.096827e+01 facet normal -8.396846e-02 9.964684e-01 0.000000e+00 facet.
- 0.815358 0.435818 0.381123 facet normal.