Labels Milestones
BackHref="https://gitea.circuitlocution.com/synth_mages/MK_VCO/commit/5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2">5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request 'new_footprints' (#5) from new_footprints into main v1 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about wiring SW15 cross-board Add design rules for jlcpcb 4ee6887723 Add some perfboard sections, power headers, teardrops checkpoint before getting really weird with WireIt A couple more GND-stitch vias Undo converting GND to GND_JMP and fix everything that broke 3583986e89 Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1. This needs to be tuned further. Licence You can use.
- Http://www.philmore-datak.com/mc/Page%20197.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO.
- Vishay, IM-10-37, http://www.vishay.com/docs/34030/im10.pdf Inductor Axial series Axial.