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BackReplaces FIREBALL mask/etch with silkscreen From c4e1c30b9b25348d7c704a6560eec4b96105b036 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add jlc constraints DRC; replace order number text replaces FIREBALL mask/etch with silkscreen adds ideas for a clock on the 16-pin IDC connector when nothing is plugged into it. - Manual offset knob From aa199fc6f4983bb3329ebb61d633face7f24ca94 Mon Sep 17 00:00:00 2001 .../Panels/UNSEEN SERVANT.png | Bin 0 -> 578884 bytes .../Panels/Radio_shaek_standoff_thick.stl | Bin 0 -> 328607 bytes Images/PXL_20210831_001017829.jpg | Bin 0 -> 11930 bytes 3D Printing/Rails/36hp_innie.stl Normal file Unescape "Name": "Top Solder Paste" "Name": "Top Solder Paste" "Name": "Bottom Silk Screen" "Name": "Top Solder Paste" "Name": "Top Silk Screen" Hardware/Panel/precadsr-panel/precadsr-panel-cache.lib Normal file Unescape Schematics/SynthMages.pretty/SOCKET_2_PIN_Header.kicad_mod Normal file Unescape Schematics/Unseen Servant/Unseen Servant.kicad_sch | 1120 From 1ed9d69b418eb6a9322b9893aea438f59933f7f4 Mon Sep 17 00:00:00 2001 Subject: [PATCH 08/18] couple more GND-stitch vias Undo converting GND to GND_JMP and fix everything that broke Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1. This needs to be even. Odd values are -=1 difference() { difference() { union() { difference(){ color([.1,.1,.1]) panel(width); scale([.38,.38,-.005]) surface("FireballSpellVertSmaller.png", center=true, invert=false); More experimentation with panel alignment before printing f6c7924538ef12da2abc179ebcc8f08e4164e698 main synth_tools/Schematics/SynthMages.pretty/eurorack_rail_hole.kicad_mod 24 lines Binary files /dev/null and b/Futura Heavy BT.ttf | Bin 16561 -> 0 bytes Latest commits for file Schematics/SynthMages.pretty/6.3mm_NPTH_MAXJLCPCB.kicad_mod Latest commits for file Examples/precadsr.pdf Binary files a/3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/BLADE BARRIER.png and /dev/null differ main MK_VCO/Fireball/Fireball.kicad_pcb 35767 lines da12ac6a39 Delete '3D Printing/Panels/FIREBALL VCO.png' 3D Printing/Panels/FIREBALL VCO.png create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/C_Rect_L7.2mm_W2.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2.kicad_mod create mode 100644 Images/PXL_20210831_001017829.jpg create mode 100644 Panels/luther_triangle_vco_quentin_v3_blank.stl.stl create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Single_Vertical.kicad_mod create mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pretty/Bigger_Push_Switch_Hole.kicad_mod delete mode 100644 Hardware/Panel/precadsr_panel_al/fp-lib-table delete mode 100644 Panels/Font files/futura medium condensed bt.ttf Normal file View File Hardware/Panel/precadsr_panel.svg Normal file View File 3D Printing/Rails/36hp_outie.stl | Bin 12821 -> 0 bytes From 2bb058d5715f395d3571ea05d3008566787a2bdb Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add CV in to pause the clock and keeps current gate open whenever the voltage exceeds a certain threshold (perhaps useful for non-browser users if (preg_match("@.*(
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