3
1
Back

Thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline (SM) - 5.28 mm Body [LFCSP]; (see https://www.intersil.com/content/dam/Intersil/documents/l72_/l72.10x10c.pdf LFCSP VQ, 48 pin, exposed pad: 4.5x8.1mm, (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/ Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias in pads, 6 Pins (https://www.molex.com/pdm_docs/sd/026605050_sd.pdf), generated with kicad-footprint-generator Tantalum Capacitor SMD AVX-U (7361-438 Metric.

New Pull Request