X="3.7" y="2.0"/> Update luther's layout organize a bit with a rock/reggae rhythm on the 16-pin IDC connector when nothing is plugged into CLOCK. Could replace step IDs with a full bridge rectifier; could use fewer caps that way 7022ad9ddb couple more minor clearance tweaks Add ground fills, fix some clearance issues, make all power traces large "rules": { PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces PCB initial layout, no traces }, More tweaks after pro review "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, "diff_pair_width": 0.2, "line_style": 0, "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.25, "via_diameter": 0.8, "via_drill": 0.4, More tweaks after pro review "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", "no_connect_dangling": "warning", "pin_not_connected": "error", "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", "similar_labels": "warning", More tweaks after pro review "design_settings": { "defaults": { PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces Fireball/Fireball.kicad_prl | 2 | 47k | Resistor | | | | C6, C7, C8, C9 Schottky Barrier Rectifier Diode, DO-41"/> Standard switching diode, DO-35"/>
Normal 0.5 -0.866025 0 facet normal 9.862182e-01.