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Back########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= b1fcba1e78f37669542b35a3e32a5257c5c0240c 744b72ef7e0d94fccfae99ec3cb3514981ac4616 bacdac34d747275148c56e8293dc209c2e326fe4 0d3d72c49e606725216a5a9a4217e6c039d5a574 d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Use THT electrolytics, finish SMT layout, try on.
- THT AT310 10.0mm-10.5mm length 3.0mm.
- Normal -0.865129 0.462436 0.19418 facet.
- Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-PasteTop.gtp create mode 100644 Panels/luther_triangle_10hp.stl.