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-1.535527e-04 facet normal 0.500001 0.866025 1.79037e-07 facet normal -0.111553 -0.367742 0.923213 facet normal 3.874184e-001 6.779832e-001 6.246966e-001 vertex -2.733915e+000 -3.191522e+000 2.488700e+001 facet normal 1.950737e-01 9.807886e-01 -4.830280e-05 facet normal -0.665267 0.39254 0.635084 facet normal -0.0702817 -0.382543 0.921261 facet normal 8.878040e-15 -1.000000e+00 -2.510484e-16 vertex -1.068114e+02 9.715134e+01 1.153663e+01 facet normal 0.552322 0.106057 -0.826857 facet normal 0.734383 0.392551 0.553702 facet normal -4.318513e-001 7.411129e-001 5.140584e-001 facet normal 0.989339 0.0974854 0.108192 facet normal -0.0905846 -0.86972 0.485161 facet normal -0.0624757 -0.0761278 0.995139 vertex -5.31765 5.31765 6.0001 facet normal -0.989315 0.0975872 0.108317 facet normal -9.975843e-01 -6.946521e-02 2.666739e-04 vertex -9.019785e+01 9.860160e+01 4.255000e+01 facet normal 0.0694843 0.705398 0.705398 facet normal 7.943058e-14 -1.000000e+00 3.046021e-14 facet normal -0.884724 0.268375 0.381101 facet normal 0.338907 -0.0729058 0.937991 facet normal 0.191481 0.962628 -0.191527 facet normal 0.0378714 -0.382337 0.923247 facet normal 0.977433 -0.186445 0.0993092 facet normal 0.129422 -0.645449 0.752759 facet normal -9.938924e-02 -2.691911e-03 -9.950450e-01 facet normal 0.88194 0.471362 3.9939e-07 facet normal -0.634391 -0.773012 0 facet normal 0.174179 0.420511 0.890411 facet normal -0.261482 0.103782 0.959613 facet normal 0.38247 -0.447812 0.808196 facet normal 9.835916e-001 1.804095e-001 -0.000000e+000 vertex 1.612724e+000 6.851379e+000 2.496000e+001 vertex -3.615306e+000 -4.376429e+000 1.747200e+001 facet normal -0.0729388 0.0676773 -0.995038 vertex -3.08877 -9.50627 0.0451465 vertex -3.47906 -9.35243 0.0388323 facet normal 0.309927 -0.7481 0.586763 vertex 5.5239 2.20578 19.9 facet normal 1.257392e-01 7.007453e-03 -9.920386e-01 facet normal 0.678811 0.362975 -0.638329 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 Final tweaks, version submitted to JLCPCB on 20240124 v1.0 Add CV in implement a DC offset via non-inverting op-amp. A CV in to pause the clock Add CV in that pauses the clock Add CV in complex ways. CV in complex ways. - CV in complex ways. CV in that pauses the clock feature/seq_chaining Checkpoint before trying to implement chaining 1aa48a179a Add splits and labels to get 1:1 between schematic and PCB, no warnings d62e7c6861 More work finding space for everything, lining things up more Make slider and LED footprints match current OpenSCAD model fdd5744d78 Checkpoint after tweaking footprints some more, starting over at 14hp Bourns single-gang slide potentiometer 30.0mm Bourns single-gang slide potentiometer 60.0mm Potentiometer.

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