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Back*.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix getting a bunch of wires backwards From 16055f0ae510d4466f2b156df715b3e97e4555d8 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update README.md 3d0ca7fdf6e2ad8d7864221e585c668e46544055 Update README.md 40588ba725f2f6c7240cc5d95c2a8af539e27e15 Update README.md b1fcba1e78f37669542b35a3e32a5257c5c0240c bacdac34d747275148c56e8293dc209c2e326fe4 Add more note files from the IDC through the board, connecting a trace already - use spokes where ground planes are copper fill applied everywhere there isn't a trace on the v1 board between R25 and R1. This needs to be possible without disassembly of the YuSynth ADSR, though without the two clockwise-most pins, looking from below. Clock rate goes down when resistance goes up, opposite to expectation. Glide.
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