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Back(31 B.Cu signal hide (31 B.Cu signal hide (33 F.Adhes user hide (0 "F.Cu" signal (31 B.Cu signal hide (31 B.Cu signal hide (33 F.Adhes user hide (37 F.SilkS user hide (42 Eco1.User user hide (37 F.SilkS user hide (35 F.Paste user (36 "B.SilkS" user "B.Silkscreen" (37 "F.SilkS" user "F.Silkscreen" (38 "B.Mask" user (39 F.Mask user (40 Dwgs.User user (41 Cmts.User user (42 Eco1.User user (43 Eco2.User user (44 Edge.Cuts user (45 Margin user (46 "B.CrtYd" user "B.Courtyard" (47 "F.CrtYd" user "F.Courtyard" (48 "B.Fab" user (49 F.Fab user (aux_axis_origin 0 0 Yet more ways of pulling comics, alt text and salient bits of blogs into Tiny Tiny RSS entries. # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: https://kicad.org/help/file-formats/ # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 0 Minor layout tweaks Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 659884 bytes Panels/title_test_22.stl.
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