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Back# drill/hole size condition "A.Type == 'pad' && B.Type == 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; FORMAT={-:-/ absolute / inch / decimal} Schematics/schematic_bugs_v1.txt Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-F_Paste.gbr Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al.sch Normal file Unescape Schematics/SynthMages.pretty/Perfboard_2x12.kicad_mod Normal file Unescape Synth Mages Power Word Stun Panel.kicad_prl create mode 100644 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/BLADE BARRIER.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin' d8a7439c05979d3c73da6a91162e90a1a48a57e5 Upload files to '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/HOLD PORTAL.png' Delete '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/POLYMORPH.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/HOLD PORTAL.png' 06850ab67823ca6e309908fccf0dcf41bca709a5 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/PRISMATIC SPHERE.png' 9bb3093b2b Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin' main synth_tools/Schematics/SynthMages.pretty/Jack_3.5mm_QingPu_WQP-PJ398SM_Vertical_CircularHoles_Socket_Centered.kicad_mod 100 lines main synth_tools/Schematics/SynthMages.pretty/3.5mm_jack_hole_nonpcb.kicad_mod 24 lines Binary files /dev/null and b/caixa_sr1.png differ Binary files a/3D Printing/Panels/image.png and /dev/null differ Latest commits for branch v1.1 Finish PCBs d74befe391233bd8b162f7f5705c277e04d9b135 Checkpoint after converting most things to SMD Binary files /dev/null and b/Panels/FireballSpellVertSmall.png differ Binary files /dev/null and b/Panels/a_color_icon_of_a_flying_fireball.webp differ Binary files /dev/null and b/Images/PXL_20210831_004139245.jpg differ Images/befaco_vcadsr.png Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: =============================================================