3
1
Back

4.5x7mm (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-71/ Infineon SO package 20pin, exposed pad (http://cds.linear.com/docs/en/datasheet/34301fa.pdf SSOP 0.65 exposed pad - Ref http://pdfserv.maximintegrated.com/land_patterns/90-0349.PDF DFN, 10 Pin (https://fscdn.rohm.com/en/techdata_basic/ic/package/Jisso_MLGA010V020A-1-2_Rev005s_E2(MSL3).pdf ST HLGA, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3471fb.pdf#page=15), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 32 Pin (https://www.jedec.org/standards-documents/docs/mo-142-d variation.

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