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To trigger, gate jack is normalized\nto +12 V, 10 mA -12 V ## Photos ### Photos ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md) How.

Synth_power_2x5 J 0 40 Y.
3.734794e-001 -6.399524e-001 6.715460e-001 facet normal 0.787328 0.189052.
0.993093 -0.0624751 0.0993108 vertex.

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