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Vertex 2.286077e+000 6.660499e+000 9.983999e+000 vertex -4.621885e+000 3.208877e+000 9.983999e+000 vertex 6.105788e+000 -3.657241e+000 1.747200e+001 facet normal 0.471404 -0.875977 0.102188 facet normal 9.106134e-01 -1.135808e-03 4.132577e-01 facet normal 0.796853 0.241727 0.553709 facet normal 0.049906 -0.0857116 0.995069 vertex -4.70605 8.15112 20.0916 facet normal -0.876745 -0.468624 0.108209 vertex 5.71086 1.13596 21.335 facet normal -9.999660e-001 -8.246416e-003 0.000000e+000 vertex 4.403623e+000 -3.613747e+000 1.747200e+001 facet normal 0.0502428 -0.08702 0.994939 vertex -4.28928 -6.75883 19.9502 facet normal 0.0765948 0.956711 0.280779 facet normal 0.0973966 -0.989347 0.108199 facet normal 0.308982 0.0243228 0.950757 vertex 3.17541 0 18.9636 facet normal -0.195101 -0.980783 -5.85608e-06 vertex 0.4 2.86172 18.9065 facet normal -0.840156 0.533176 0.0993072 facet normal 0.630715 -0.768435 0.108196 facet normal 9.513532e-01 -1.155796e-03 -3.081003e-01 facet normal -0.714676 -0.586516 0.3811 vertex 7.38961 6.86157 2.58057 facet normal -5.032444e-001 8.627504e-001 4.905997e-002 facet normal 9.924581e-01 4.345032e-03 1.225072e-01 facet normal -0.0819688 -0.0815293 0.993295 vertex -4.10478 -5.1829 7.85113 facet normal 0.847857 0.479705 0.225879 facet normal 4.050273e-01 9.143046e-01 8.142858e-05 vertex -9.465500e+01 1.055561e+02 4.255000e+01 facet normal 9.062919e-001 4.035546e-003 4.226331e-001 vertex -5.033847e+000 -2.117175e+000 2.480400e+001 facet normal 4.942510e-001 8.649395e-001 8.715332e-002 facet normal 0.292559 -0.954686 0.0546222 facet normal -0.334131 -0.539147 0.773096 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository https://github.com/holmesrichards/precadsr Submodules Latest commits for file Fireball/Fireball.kicad_sch Added input resistor for sync; placed everything on PCB with exploratory 8hp layout Bring in diylc and openscad design ## Mechanical assembly Documentation # ---> KiCad # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Minor layout tweaks merged pull request 'Finish schematic, add PDF Fix for two bugs in Doghouse Diaries rss: spaces in img src and quotes in alt/title text under images (extra useful for non-browser users 1e6cc98f41 Various updates, additions Updated LICD, alter alt-textify to handle both title and alt tags elseif (strpos($article['content'], 'invisiblebread.com/2') !== FALSE) { // Two Lumps // Breaking Cat News elseif (strpos($article['link'], 'somethingpositive.net') !== FALSE) { elseif (strpos($article['link'], 'http://www.geekculture.com/joyoftech/') !== FALSE) { // Questionable.

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