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File 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-F_Paste.gbr Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-job.gbrjob Normal file View File From 4049c4aafe61a54c756e746df9f3a582c255b776 Mon Sep 17 00:00:00 2001 Subject: [PATCH] AD&D 1e MM, DMG, and PHB. Panels/Futura XBlk BT.ttf From f80e4975fbba2affa8a7d947f9ed8429315837d4 Mon Sep 17.

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