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Ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Latest commits for branch corrected_silkscreen updated README.md README.md | 2 Fireball/Fireball.kicad_pro | 8 | 1N4148 | 100V 0.15A standard switching diode, DO-35 2x5 pin shrouded header 2.54 mm spacing | Tayda | A-553 | | | | R8, R10, R12 | 3 | 4.7k | Resistor | | | S2 | 1 | B20k | Potentiometer | | J9 | 3 | 22k | Resistor | | | D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 | 8 "use_height_for_length_calcs": true From cb3a50e19a42a9ab425057cfa1f9427c1c21d019 Mon Sep 17 00:00:00 2001 Panels/FIREBALL VCO.png .

MS-013AD, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_wide-rw/RW_24.pdf), generated with kicad-footprint-generator.
12.2mm Capacitor C, Rect.
5.000001e-001 8.660254e-001 0.000000e+000 vertex 3.826173e+000 -4.223009e+000 2.496000e+001.

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