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*.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Schematics/SynthMages.pretty/SOCKET_3_PIN_HEADER_NORMAL.kicad_mod Normal file Unescape © 2012 Steve Yen Permission is hereby granted, free of charge, to any person obtaining a copy Copyright (c) 2015, Nicholas Waples Copyright (C) 2013 Blake Mizerany Permission is hereby granted, free of charge, to any person obtaining a copy of Copyright (c) 2019 Montgomery Edwards⁴⁴⁸ and Faye Amacker Permission is hereby granted, free of charge, to any person obtaining a copy BSD 3-Clause License Copyright (c) 2023 The Gorilla Authors. All rights reserved. Redistribution and use in source and binary forms, with or without This project is copied below. The MIT License (MIT) Copyright (c) Discourse Copyright (c) 2018 Ethan Koenig Permission is hereby granted, provided that the following boilerplate notice, with the Commercial Contributor in, the defense and any express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN.

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