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Back[How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about UX component wiring D36/R47 too close Testing before powering up: Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 Clock Rate - variable resist +6k between U2-8 and U2-9 Reset Sw - when pressed, short +12V and Reset In Pause CV In Latest commits for file Fireball/Fireball.kicad_pro Latest commits for file Synth Mages Power Word Stun Panel.kicad_prl main synth_tools/Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod 66 lines 811ef45c76 schematic start, and some example modules Envelope/Envelope.kicad_pcb | 2 | 10uF | Polarized capacitor | | | | Tayda | A-1847 | | S2 | 1 | Conn_01x10 | Pin header, 2.54 mm, 1x10 | | | | | | J5, J12, J13 | 3 | 10uF | Electrolytic capacitor | | | | | J1 | 1 Hardware/lib/aoKicad | 1 | Conn_01x02 | SIP socket, 2.54 mm, 1x2 (see [build notes](build.md)) | | | | | | L1 | 1 | Conn_01x02 | SIP socket, 2.54 mm, 1x10 | | | | | C1 | 1 | 10 nF Docs/precadsr.pdf | Bin 0 -> 113418 bytes create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Single_Vertical.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PPTC_RXEF025.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Arduino_Nano.kicad_mod create mode 100644 Schematics/SynthMages.pretty/3.5mm_jack_hole_nonpcb.kicad_mod create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-EdgeCuts.gm1.
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