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Back100644 Hardware/PCB/precadsr/precadsr.kicad_pro create mode 100644 Schematics/SynthMages.pretty/Micro SPDT (3 pin).kicad_mod main precadsr/Docs/build.md 65 lines # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated.
- 0.257269 0.262733 0.929938 facet normal 0.0815519 0.0814596.
- Normal 6.034096e-17 -5.396832e-16 -1.000000e+00 facet normal.