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BackSchematics/bad_trace_v1.jpeg | Bin 0 -> 11692 bytes .../HOLD PORTAL.png | Bin 11675 -> 0 bytes Binary files /dev/null and b/3D Printing/Rails/36hp_innie.stl differ Binary files /dev/null and b/Panels/futura medium bt.ttf From 4d5fa6d9031cd3c77276604f864cee7dad9fcfbf Mon Sep 17 00:00:00 2001 Subject: [PATCH] A couple more GND-stitch vias Undo converting GND to GND_JMP and fix everything that broke 3583986e89 Finished PCB, passes all passable DRCs Footprint selection, some PCB layout choices From c6741b48f0ef8a6e69ecbca1a47bc4f4b481e2a3 Mon Sep 17 00:00:00 2001 Subject: [PATCH 18/18] Final revision; added custom DRC as project file ) ) ) ) Final revision; added custom DRC as project file 8976a63dc06fa25beedf8d2553931872c491047e adds README.md file 8976a63dc06fa25beedf8d2553931872c491047e adds README.md file 33729ec97f6dd2ed68c4ca06088ce0b21651948d Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane Updates from real TL0x4, fix pots being backwards, tighten up schematic, fit letter instead of A4 More cleanup
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