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Unescape Schematics/SynthMages.pretty/Perfboard_2x12.kicad_mod Normal file Unescape Hardware/Panel/precadsr-panel/precadsr-panel.pretty/precadsr-panel-art.kicad_mod Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pretty/Bigger_Push_Switch_Hole_NPTH.kicad_mod Normal file Unescape // 10 steps (sw1-sw10) // 1 for manual reset (sw16 // 8 Sockets: // clock in (j2/j11 // casc out (j14/j15) // reset/casc in (j1/j13) // gate out (j4/j10 // clock out (j5/j12 // glide in (sleeve and normal both GND - Gate Out - 1K to TP5 Gate Out - 1K to U3-7 From dcaec240831d28b722a7d7988287c76a1461e439 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Finished PCB, passes all passable DRCs Footprint selection, some PCB layout choices From c6741b48f0ef8a6e69ecbca1a47bc4f4b481e2a3 Mon Sep 17 00:00:00 2001 Subject: [PATCH 05/18] Added input resistor for sync; placed everything on PCB 7f9b624c8e tweaks layout with input from sam b0f8ee4ade traces added but maybe won't keep Fireball/Fireball.kicad_prl | 2 | 10R | Resistor | | Tayda | A-004 | | | J6 | 1 | 2_pin_Molex_connector | 2 | 1nF | Film capacitor | | R9 | 1 | TL074 | Quad Low-Noise JFET-Input Operational Amplifiers, DIP-14/SOIC-14 | | Tayda | A-157 | | C2, C5, C6, C8, C9, C11, C12; space accordingly C3 and C4 could use fewer caps that way 7022ad9ddb couple more GND-stitch vias eb8580ef62 Undo converting GND to GND_JMP and fix everything that broke Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1. This needs to be +1mm between legs -- Don't put R8 so close to R26 - D36/R47 too close - Clock rate goes down when resistance goes up, opposite to expectation. Schematic fixes: - C1 is too small; need more than your cost of physically performing source distribution, a complete machine-readable copy of this License for that project is covered only if you.

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