synth_tools

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-0.533195 0.0992474 facet normal 0.264755 0.918689 0.293113 vertex -4.13938 5.6469 10.3435 facet normal 0.631387 0.769304 0.0975749 vertex 5.00013 7.48323 3 facet normal -4.978804e-001 -8.663539e-001 3.931974e-002 facet normal -0.564081 -0.273132 0.779238 facet normal 0.491352 0.598708 0.632552 vertex 7.27387 -4.86024 5.33536 facet normal -0.241727 -0.796853 0.553709 facet normal 1.028882e-001 9.946929e-001 -0.000000e+000 vertex 2.937280e+000 6.404036e+000 1.747200e+001 facet normal -0.250125 0.625096 0.739387 facet normal 0.000000e+00 -1.000000e+00 vertex -1.095272e+02 9.665134e+01 1.561034e+01 vertex -1.095272e+02 1.011513e+02 2.550000e+00 facet normal 0.309927 -0.7481 0.586763 vertex 3.2761 -2.20578 19.9 vertex 1.92439 0 19.9 facet normal 5.735811e-001 2.553783e-003 8.191448e-001 facet normal 4.928424e-001 -8.701186e-001 0.000000e+000 vertex -6.672863e+000 -2.335454e+000 2.496000e+001 vertex -1.118343e+000 -5.580715e+000 9.983999e+000 vertex 3.858692e+000 5.902027e+000 9.983999e+000 vertex -6.866518e+000 -1.662893e+000 1.747200e+001 vertex -6.149543e+000 3.418378e+000 1.747200e+001 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF Features already done: Internal clock with manual control. Clock in socket with 80 contacts AT ISA 16 bits Bus Edge Connector BUS ISA AT Edge connector PCI bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70 Highspeed card edge connector for PCB's with 08 contacts (not polarized Connector PCBEdge molex EDGELOCK.

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