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Back0,0,h0], [ ord*cos(lf0), ord*sin(lf0), h0], [ ird*cos(lf0), ird*sin(lf0), h1], [ ird*cos(lf2), ird*sin(lf2), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: ============================================================= d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Start of LM13700 version to see why 0d3d72c49e Use THT electrolytics, finish SMT layout, try on quentin font Schematics/Enlarge/Enlarge.kicad_prl | 77 Fireball/Fireball_panel.kicad_pro | 504 Fireball/fp-info-cache | 51 ...D_DO-41_SOD81_P7.62mm_Horizontal.kicad_mod | 51 .../Jack_6.35mm_PJ_629HAN.kicad_mod | 29 aoKicad | 2 | 1 | B10k | \*\*Potentiometer, 9 mm or 16 mm 3.5 mm jack 3 mm LED 5 mm | | | J7 | 1 | 10R | Resistor | | | R24, R26, R28 | 4 .../PCB/precadsr_Gerbers/precadsr-F_Paste.gbr | 4 | 47k | Resistor | | | | | | J2 | 1 | Conn_01x07 | \*(optional) SIP socket, 2.54 mm, 1x10 | | | J2 | 1 | 2_pin_Molex_header | KK254 Molex header 2.54 mm 2x5"/>